Chip Design of an Analog Low Power Sum-Product LDPC Decoder using Early Termination

• Main Authors: Yu-Shi Ke, 柯玉璽
• Other Authors: 李文達
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/dvtt8g

碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 101 === This thesis proposes an analog low power LDPC decoder employing new stopping iteration method. It is based on the sum-product algorithm and by checking parity H-matrix to decide iteration termination. The supply voltage of the proposed decoder only uses 1.2V not 1.8V, so the power consumption can be reduced significantly, and then 76% power consumption is saved. Moreover, the early termination method is used. It not only can increase the decoding throughput but also save the power consumption. With these improvements, a very low energy efficiency 7.57pJ/b is obtained when throughput is 31.72Mbps. Finally, an analog low power sum-product LDPC decoder using early termination is implemented by TSMC 0.18μm 1P6M CMOS technology. The chip size is only 0.08mm2 without I/O pad and gate count is 2490. The proposed decoder has very low energy efficiency and low chip area characteristics. So it can be applied to the mobile devices and SoC system.