| Summary: | 博士 === 國立雲林科技大學 === 工程科技研究所博士班 === 101 === Along with the advance in consumer electronics and communication technologies, high speed data converters were applied to many applications. The data converter testing is one of the most challenging problems in the area of analog and mixed-signal testing. As an interface between digital systems and analog world, the digital to analog converter (DAC) is one of the most widely used mixed-signal integrated circuits. Conventional DAC test methods require measurement equipments with higher speed than the circuit under test to sample and characterize the performance of the circuit accurately. Consequently, the design and manufacturing of instruments is really a challenge and extremely difficult for those high speed DACs. In addition, even worse, interference and noise in test environment also make test result distortedly.
To enhance the testability, built-in self-test (BIST) is the promising way to measure analog signal in chip accurately. However, due to the heat originated from continuous high speed operation of the circuit under test, the characteristics and functions of BIST circuit may drift according to the temperature variation of chip. For advanced fabrication process with shorter transistor channel length, the temperature dependence is more serious because of acute impact on carrier mobility and threshold voltage. The BIST circuit could be out of controlled or unavailable for the worst.
For this reason, this dissertation presents a BIST scheme for estimating the nonlinearity errors of DAC and employs well-developed low thermal sensitivity processing circuits to enhance the reliability of testing results as well. Through applying dual-under-sampling approach and pulse-width-modulation (PWM), the DAC output signal is modulated into low-speed narrow-width pulse streams. The nonlinearity errors of DAC are proportional to pulse width of modulated signal which can be quantified as digital representation. To enhance the accuracy of modulators for PWM, a current-mode comparator is proposed instead of voltage-mode comparator. A cyclic time-to-digital converter (TDC) is also proposed to measure the pulse width of signal on chip. All of the crucial circuits are designed with temperature compensation technique, so that the measurement error can be reduced when the temperature varies with continuous operation of DAC at high speed test.
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