Dual Bit-Rate Burst-Mode Clock and Data Recovery Circuit based on DLL
碩士 === 國立雲林科技大學 === 電機工程系碩士班 === 101 === The main purpose of this paper is to describe how dual bit-rate burst-mode clock and data recovery circuit be achieved with delay-locked loop. The basic introduction and some considerations of CDR would be presented at the beginning. Then, a few common archit...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/75395291274274103557 |