Zero-One LFSR for Low Power Deterministic BIST
碩士 === 元智大學 === 資訊工程學系 === 101 === Power consumption and test data volume are two important issues in VLSI testing. BIST (Built-In Self-Test) is a kind of DFT technique, which uses embedded logic gates to detect some faults in circuits. LFSR is commonly used in low overhead BIST to generate test dat...
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| Format: | Others |
| Language: | zh-TW |
| Online Access: | http://ndltd.ncl.edu.tw/handle/16699935816701237498 |
| Summary: | 碩士 === 元智大學 === 資訊工程學系 === 101 === Power consumption and test data volume are two important issues in VLSI testing. BIST (Built-In Self-Test) is a kind of DFT technique, which uses embedded logic gates to detect some faults in circuits. LFSR is commonly used in low overhead BIST to generate test data. In this thesis we partition the scan chain in two subscan chains, one with most zeros and the other with most ones of testing data. We use one LFSR set to generate the most zero scan chain by AND operation and the other generate the most one scan chain by OR operation to achieve low power consumption and data compression effect. Experimental results by applying the proposed approach to ISCAS89 circuits shows that a good test data volume reduction as well as power reduction can be achieved significantly.
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