Interference-aware Batch Memory Scheduling in Heterogeneous Multicore Architecture
碩士 === 國立中正大學 === 資訊工程研究所 === 102 === In recent years, integrating Central Processing Units (CPUs) and Graphics Processing Units (GPUs) on the same chip has become a major trend. For instance, the Heterogeneous System Architecture (HSA) has been proposed as an integrated architecture that combines C...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/58662903211578321211 |