| Summary: | 碩士 === 國立中正大學 === 資訊工程研究所 === 102 === Phase-locked loop (PLLs) are widely used in a system-on-a-chip (SoC). In contrast to analog PLLs, all-digital phase-locked loops (ADPLLs) use digital design approaches which allows it to be easily integrated with other digital circuits into the systems in advanced CMOS process. In order to reduce the design time and design efforts when processes or specifications are changed, ADPLLs which implemented with standard cells have best portability and suitable for the SoC as compared with analog PLLs.
Among the functional blocks of the ADPLL, digitally controlled oscillator (DCO) is the most critical component. Because the DCO usually occupies the most portions of the chip area and consumes relative large power consumption than the other blocks of the ADPLL. Furthermore, DCO dominates the major performance of the ADPLL, such as the output frequency range, and output jitter. According to different design requirements for realizing an ADPLL for various applications, such as a spread-spectrum clock generator (SSCG), a fast settling ADPLL, an automatic design flow for the ADPLL is demanded in order to speed up the overall design process and reduce design turnaround time.
Traditionally, PLL usually takes long lock-in time. Thus for power management of the SoC, PLL can’t be turned off for reducing the standby power consumption. The continuous operating PLLs often dominate the standby power consumption of the system. If the PLL can quickly achieve lock-in and then the PLL can be turned off for reducing energy consumption.
Therefore, an ADPLL which has a fast settling that generated by an ADPLL compiler with liberty timing files is presented in this thesis. The proposed ADPLL has following characteristics: fast lock-in time, low power consumption and a flexible DCO architecture with high linearity. In addition, the test chip is implemented and tapeouted in 90nm CMOS process to verify the proposed ADPLL compiler.
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