A 10Bit 100MS/s With Stay&Inverse switching Multi-Bit Successive Approximation ADC
碩士 === 國立中正大學 === 電機工程研究所 === 102 === A 10Bit 100MS/s with Stay&Inverse multi-bit successive approximation analog-to-digital converter(SA ADC) is proposed and implemented.The converter is implemented by TSMC 90nm CMOS process technology. At 100MS/s, the ADC achieves an SNDR of 59.833dB and consu...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/cdthqy |