The Study of Warpage Simulation of Wafer Processing

碩士 === 中華大學 === 機械工程學系碩士班 === 102 === Electronic Packaging reliability is of great concern to semiconductor and electronic product manufacturers. From the first to the fourth generation computer, the tremendous growth of computers and 3C products, and its significant impact on our lives is the inven...

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Main Authors: Cheng, pen-nung, 鄭本農
Other Authors: Chen, Ching-I
Format: Others
Language:zh-TW
Published: 2014
Online Access:http://ndltd.ncl.edu.tw/handle/04876770022028255303
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spelling ndltd-TW-102CHPI54890162017-02-17T16:16:38Z http://ndltd.ncl.edu.tw/handle/04876770022028255303 The Study of Warpage Simulation of Wafer Processing 晶圓製程之翹曲研究 Cheng, pen-nung 鄭本農 碩士 中華大學 機械工程學系碩士班 102 Electronic Packaging reliability is of great concern to semiconductor and electronic product manufacturers. From the first to the fourth generation computer, the tremendous growth of computers and 3C products, and its significant impact on our lives is the invention of the microprocessor. Wafer level packaging is an important development trend for IC package design. Warpage problem plays an important role in IC encapsulation processes. A few researchers studied the warpage analyses with temperature changes in particular process in steady of the whole wafer processes. The purpose of this research is to analysis of the wrapage of the CMOS in each manufacture process by finite element method. In finite element model, there are three models: (a) 8 inch wafer with chip size (6370 m×7194.8 m); (b) 8 inch wafer with chip size (2560 m×2520 m); (c) 12 inch wafer with chip size (2560 m×2520 m). Due to the different processes and the dimension scale of different components, the Ealive and Ekill and the submodel technique are used. From global model to four submodels, the wrapage simulation in wafer level to die level is achived. Finally, the Si layer and Al layer equivalent stresses in die level at different locations, inner, middle and outer, are derived. According to the results, the wrapage between model A and model B is not consequence with respect to die size. However, the wrapage of model C is two times of that of model A. For 8 inch, the equivalent stress of Si layer at outer is 5.61 % greater than that of at inner and the equivalent stress of Al layer at outer is 3.36 % greater than that of at inner. For 12 inch, the equivalent stress of Si layer at outer is 6.64 % greater than that of at inner and the equivalent stress of Al layer at outer is 1.88 % greater than that of at inner. Chen, Ching-I 陳精一 2014 學位論文 ; thesis 49 zh-TW
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description 碩士 === 中華大學 === 機械工程學系碩士班 === 102 === Electronic Packaging reliability is of great concern to semiconductor and electronic product manufacturers. From the first to the fourth generation computer, the tremendous growth of computers and 3C products, and its significant impact on our lives is the invention of the microprocessor. Wafer level packaging is an important development trend for IC package design. Warpage problem plays an important role in IC encapsulation processes. A few researchers studied the warpage analyses with temperature changes in particular process in steady of the whole wafer processes. The purpose of this research is to analysis of the wrapage of the CMOS in each manufacture process by finite element method. In finite element model, there are three models: (a) 8 inch wafer with chip size (6370 m×7194.8 m); (b) 8 inch wafer with chip size (2560 m×2520 m); (c) 12 inch wafer with chip size (2560 m×2520 m). Due to the different processes and the dimension scale of different components, the Ealive and Ekill and the submodel technique are used. From global model to four submodels, the wrapage simulation in wafer level to die level is achived. Finally, the Si layer and Al layer equivalent stresses in die level at different locations, inner, middle and outer, are derived. According to the results, the wrapage between model A and model B is not consequence with respect to die size. However, the wrapage of model C is two times of that of model A. For 8 inch, the equivalent stress of Si layer at outer is 5.61 % greater than that of at inner and the equivalent stress of Al layer at outer is 3.36 % greater than that of at inner. For 12 inch, the equivalent stress of Si layer at outer is 6.64 % greater than that of at inner and the equivalent stress of Al layer at outer is 1.88 % greater than that of at inner.
author2 Chen, Ching-I
author_facet Chen, Ching-I
Cheng, pen-nung
鄭本農
author Cheng, pen-nung
鄭本農
spellingShingle Cheng, pen-nung
鄭本農
The Study of Warpage Simulation of Wafer Processing
author_sort Cheng, pen-nung
title The Study of Warpage Simulation of Wafer Processing
title_short The Study of Warpage Simulation of Wafer Processing
title_full The Study of Warpage Simulation of Wafer Processing
title_fullStr The Study of Warpage Simulation of Wafer Processing
title_full_unstemmed The Study of Warpage Simulation of Wafer Processing
title_sort study of warpage simulation of wafer processing
publishDate 2014
url http://ndltd.ncl.edu.tw/handle/04876770022028255303
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