Design of a 10-bit 100MHz Pipelined ADC

碩士 === 中原大學 === 電子工程研究所 === 102 === This paper describes a 10-bit 100Msample/s pipelined analog-to-digital converter (ADC) fabricated in TSMC 0.18um 1P6M CMOS technology. By amplifier sharing technique, the converter is realized using only four amplifiers in front of eight stage to reduce the chip a...

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Bibliographic Details
Main Authors: Hsiu-Chuan Li, 李修全
Other Authors: Chun-Chieh Chen
Format: Others
Language:zh-TW
Published: 2014
Online Access:http://ndltd.ncl.edu.tw/handle/10045794525214944702