Design of High Performance Full Adder Cores for Arithmetic Applications

• Main Authors: Chiou-Kou Tung, 董秋溝
• Other Authors: Ching-Hwa Cheng
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/258pdg

博士 === 逢甲大學 === 電機與通訊工程博士學位學程 === 102 === Since a full adder plays the most critical role in the performance of an arithmetic circuit, this dissertation aims to present three high performance full adders for the chip area and power consumption reduction, and for the improvement in robust output driving capability and modular circuit structures. They are designated as a regularly modularized multiplexer-based full adder (MUXFA), a low power high speed and low-complexity full adder (LPHS-FA), and a fully symmetric parallel full Adder (FSPFA). The MUXFA full adder is composed of three identical modules, in which each module separately operates for an XOR-XNOR function, a sum function, and a carry function. The structure of the multiplexer-based full adder can be easily constructed by merely having a single multiplexer module, the features of which include fast design time, a regular structure, a simple layout, and enhanced layout efficiency. The advantages of the design concern design simplicity, design regularity, and integrated-circuit (IC) layout modularity. These characteristics are useful and important in cell-based design, especially for increasing in IC layout efficiency. Due to the regularity and modularity, the proposed full adder uses nineteen transistors only. As compared with NEW-HPSC, Hybrid-CMOS, DPLFA and SR-CPL full adders, the transistor count is reduced from 26.3% to 47.3% and power-delay-product (PDP) is reduced from 48.4%-122%. A low-power, high-speed, and low-complexity full adder, abbreviated as LPHS-FA, is presented in this work as a detailed method to reduce its circuit complexity and to elevate its performance. Employing as few as 15 MOSFETs in total, an LPHS-FA requires 60% to 86% fewer transistors than other types of existing full adders. Compared with other types of existing full adders, an LPHS-FA is found to provide a 20.4% to 27% power saving, a 12.3% to 67.0% delay time reduction, and a 35.2% to 102% reduction in power delay product. There is no doubt that a full adder serves as the core foundation in an arithmetic circuit. For performance elevation, the FSPFA full adder performs parallel logic operations, i.e. sum and carry output operations, in a sum module and a carry module, respectively. Consequently, both the sum output (So) and the carry output (Co) can be generated in a highly efficient fashion. Although the sum and the carry modules conduct independent operations, they both share exactly the same circuit architecture. In this context, the circuit layout is simple, clean, and compact, giving rise to a direct and considerable improvement in the circuit design efficiency. In simple terms, a single circuit layout can be used for both modules, that is, approximately a 100% efficiency elevation. In comparison with the other four full adders, the FSPFA is found to provide superior performance in power consumption, delay time, and power delay product. There are three high performance full adders presented here. a MUXFA, an LPHS-FA and an FSPFA. The MUXFA has a regular modular circuit structure as well as high circuit layout efficiency. The LPHS-FA has a simple circuit configuration and reduced transistor count. The FSPFA has parallel processing, symmetrical structure, and high circuit layout efficiency. The applications of these high-performance full adders apply to any type of arithmetic systems, the total performance of the system will be directly boosted as a whole.