A 10-bit 20-MS/s Successive-Approximation Analog-to-Digital Converter with Low Capacitance Loading
碩士 === 國立高雄應用科技大學 === 電子工程系碩士班 === 102 === This thesis presents the design of a 10-bit 20-MS/s successive-approximation (SAR) analog-to-digital converter (ADC). The comparator-based switched capacitor (CBSC) amplifier circuit and an active charge transferring structure are proposed to reduce the cap...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/jzkwbj |