An Improvement on Wafer Edge Defects & Arcing Issues Reductions in Etching Processes

• Main Authors: HUANG, SHIH-WEI, 黃世偉
• Other Authors: Te-Jen Su
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/68g4zp

碩士 === 國立高雄應用科技大學 === 電子工程系碩士班 === 102 === For dielectric etching in advanced chip designs, the plasma damage phenomenon called "wafer arcing" and defects which are located at wafer edge area, are two main challenge problems. As for the arcing, it is randomly occurring and the arcing-induced particles also increase chamber contamination, requiring more maintenance and downtime. On the other hand, wafer edge defects are mostly caused by the improper parts installation methodology of the process tool. Both two issues would impact the wafer quality and yield performance. To minimize the wafer-arcing frequency and wafer edge defect levels has became a key selection criterion for dielectric-etch systems, especially in the current advance technology nodes. In this study, we propose a the new jig to standardize the parts installation procedure for the equipment engineers, to avoid the human abnormal installation issues in the tool maintenance. On the other hand, wafer-less dry clean is applied to remove the by-product from the chamber wall which is significantly improving the wafer edge defect performance. As for the wafer arcing, it is applied the continuous plasma approach to reduce the fall-on and particle concerns. Moreover, e-chuck grounding sequence is also taken to reduce the accumulation of the electric charging for the wafer arcing issue improvement. By QC-story analysis approach, we dig out the root cause firstly and then take the above proposals to collect the massive data to confirm and verify the issue is finally improved. The scrapped wafer amounts and costs are both reduced under the production line implementation.