A Throughput Driven High Level Synthesis Algorithm to Synthesize Circuits with Multiple Sampling Rates
碩士 === 國立成功大學 === 電機工程學系 === 102 === Current High-level synthesis (HLS) algorithms mainly synthesize components with single sampling rate in a single clock domain. In this work we present a novel throughput driven HLS algorithm that can synthesize a complex hardware block with multiple sampling rate...
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| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/th83r9 |
| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 102 === Current High-level synthesis (HLS) algorithms mainly synthesize components with single sampling rate in a single clock domain. In this work we present a novel throughput driven HLS algorithm that can synthesize a complex hardware block with multiple sampling rates into a design with multiple clock domains. The algorithm first profiles components in a complex hardware block and explores possible clock domains of each component. The goal is to identify the lowest possible clock rate of each component that meets the throughput constraint, thereby yielding the lowest power consumption. The buffers with optimal depth are then inserted between components to complete the design. Experimental results show that our approach achieved 87% power reduction compared to the traditional HLS approach.
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