A 0.5-to-3.0 Gb/s Dual Edge Sampling Delay-Locked Loop Based Clock and Data Recovery Circuit
碩士 === 國立成功大學 === 電機工程學系 === 102 === This thesis presents a 0.5-to-3.0 Gb/s dual edge sampling DLL-CDR for clock-embedded intra-panel interface applications. By combining the proposed dual edge sampling and half-UI embedded clock coding, the proposed DLL can save 4 times number of the required delay...
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| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/94286602300952128990 |