A 10-bit 120-MS/s SAR ADC with Compact Architecture and Noise Suppression Technique
碩士 === 國立成功大學 === 電機工程學系 === 102 === This thesis proposes three circuit design techniques for successive-approximation (SAR) analog-to-digital converters (ADCs). A single-channel 10-bit 180-MS/s asynchronous SAR ADC in 90-nm CMOS process was realized based on the proposed techniques. First, the comp...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/2hm534 |