A 10-bit Segmented Digital-to-Time Converter with 10ps-level Resolution and Automatic Offset Calibration
碩士 === 國立成功大學 === 電機工程學系 === 102 === A 10-bit segmented digital-to-time converter with 10-ps-level resolution and automatic offset calibration is proposed. The segmented architecture (2-bit binary code +8-bit thermometer code) used in digital-to-analog converters (DAC) is adopted in the proposed dig...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/ythaq7 |