Parallel Implementation for In-Loop Filter of HEVC on GPU
碩士 === 國立成功大學 === 電機工程學系 === 102 === This thesis proposes a parallel program architecture which is running on GPU and CPU to reduce execution time for in-loop filter of HEVC. The in-loop filter includes de-blocking filter and sample adaptive offset. In the de-blocking filter, we use edge-level data...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/84174104920642528922 |