| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 102 === This thesis proposes a parallel program architecture which is running on GPU and CPU to reduce execution time for in-loop filter of HEVC. The in-loop filter includes de-blocking filter and sample adaptive offset. In the de-blocking filter, we use edge-level data parallelism to filter block edges in parallel that skips quadtree decomposition algorithm and z-scan order process. For the sample adaptive offset, we divide sample adaptive offset into statistics calculation, parameters decision, and sample compensation. In the statistics calculation, we use atomic addition and parallel reduction methods to overcome the issue about parallel accumulate for memory. Moreover, we employ a function of information estimation to estimate bitrate instead of context-adaptive binary arithmetic coding for the parameters decision. Finally, the sample compensation compensates samples parallelly based on sample-level data parallelism. Experimental results show that the proposed parallel program architecture achieve 5.0 speedup for de-blocking filter and 10.5 speedup for sample adaptive offset.
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