Clock Tree Synthesis with Buffer Insertion/Sizing
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 102 === Clock tree synthesis plays a vital role to achieve a successful high performance chip design. Clock skew influences the chip performance directly. In this work, we propose a new wire resistance model based on the actual wire resistance extracted by a commerci...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/14121757176323982028 |