An Investigation on Designing a Routability Optimizer in the Post-Placement Stage
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 102 === As the technology node advances, IC design has become more complicated. The shrinkage of design is rapid. The interconnect delay already dominates the circuit delay. The scaling of interconnection oversteps the original design that the routing stage in the VL...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/74615075210525340275 |