| Summary: | 碩士 === 國立交通大學 === 電信工程研究所 === 102 === In this thesis, firstly ZrO2/Ge MOS capacitors are fabricated. ZrO2 was deposited by atomic layer deposition (ALD) with different conditions such as deposition temperatures and post deposition annealing (PDA) temperatures. We electrically and physically analyze the ZrO2/Ge MOS capacitors. Conductance method is discussed in detail and utilized to extract the density of interface state of the ZrO2/Ge MOS capacitors. Also, by using quasi-static C-V curve and Berglund integral, we can estimate the band bending efficiency from the extracted surface potential. We choose ALD at 250C and PDA at 600C in N2 ambient for one minute to be an optimized condition to fabricate the Ge MOSFETs.
Secondly, we successfully fabricate the Ge MOSFETs using a gate last scheme. The on/off ratio of our p+/n junction and reaches 1.66×104 and 2.92×103, respectively and the subthreshold swing of p-MOSFET is 119 mV/dec. The on/off ratio of our n+/p junction and n-MOSFET reaches 1.51×105 and 1.73×104, respectively and the subthreshold swing of n-MOSFET is 112.5 mV/dec. Even so, we find, however, there is a large source/drain series resistance in our MOSFET due to the dopant out-diffusion during the high- dielectric annealing. In order to improve this drawback, we further change the fabrication from the gate last scheme to the gate first scheme.
Thirdly, we fabricate Ge MOSFETs using a gate first scheme. The on/off ratio of our p+/n junction and p-MOSFET reaches 8.61×104 and 5.32×103, respectively and the corresponding subthreshold swing is 125.8 mV/dec. The on/off ratio of our n+/p junction and n-MOSFET is 1.66×104 and 3.02×103, respectively while the subthreshold swing is 130.5 mV/dec.
Finally, comparison between the studied gate last and gate first MOSFETs is discussed in detail. The engineering findings of this study indicates that source/drain series resistance can be largely reduced due to more effective dopant activation caused by the last high temperature step in the gate first process.
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