ICEPL: A thermal-aware Placement for Temperature and Thermal Gradient Minimization
碩士 === 國立交通大學 === 電信工程研究所 === 102 === We propose two thermal optimal techniques with rough legalization in flat force-directed global placement which abates both on-chip peak temperature and thermal gradient. In order to make use of thermal forces, bases of thermal space inside the chip are used to...
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| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/7uqkde |
| Summary: | 碩士 === 國立交通大學 === 電信工程研究所 === 102 === We propose two thermal optimal techniques with rough legalization in flat force-directed global placement which abates both on-chip peak temperature and thermal gradient. In order to make use of thermal forces, bases of thermal space inside the chip are used to fast and accurately capture the temperature distribution between different placement results based on thermal response method. Then and there two innate thermal forces assessed through thermal sensitivity and thermal capability are proposed to spread cells away from hotspot. The other way is thermal padding which is an effective method to conserve white space for cells with high power density so as to reduce the power density virtually; meanwhile, the dissipation space is reserved. In all experiments, the thermal simulator via thermal bases exhibits the error of 0.35% on average compared with GIT. Thermal forces provide 5.16% and 63.14% reduction on average in peak temperature and thermal gradient respectively within 10.85% wirelength overhead and thermal paddings result in an impressive reduction in peak temperature by 18.94% and thermal gradient by 93.66% within 11.88% wirelength overhead on average. By combining the two proposed methods, our experiments demonstrate that the thermal quality resulted from thermal padding could be improved by extra thermal forces.
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