All-Digital Wide-Range Pulsewidth Controlled Circuits With Programmable Duty Cycle
碩士 === 國立交通大學 === 電機工程學系 === 102 === When the operation frequency in SOC is increasing, the clock skew and pulsewidth variation may cause errors in all systems. In digital systems, many circuits, like phase-locked loop (PLL) and delay-locked loop (DLL), are required to synchronize and align clock....
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/58359500106139770699 |