| Summary: | 碩士 === 國立交通大學 === 電機工程學系 === 102 === When the operation frequency in SOC is increasing, the clock skew and pulsewidth variation may cause errors in all systems. In digital systems, many circuits, like phase-locked loop (PLL) and delay-locked loop (DLL), are required to synchronize and align clock. In order to meet the requirements of the high-speed operation for SOC systems, double date rate (DDR) technology, such as DDR SDRAM, is used to achieve the need. Because the positive and negation transition edges of the reference clock signal are utilized to sample the data in DDR technology, a precise 50% duty-cycle clock is important. With the process, voltage, and temperature (PVT) variation, it is hard to maintain 50% duty-cycle of clock signal, so many papers are committed to find a solution to meet the requirements.
In this thesis, we propose two duty-cycle correction circuits. The first one is an All-Digital Wide-Range Duty-Cycle Corrector using a Period Estimation Algorithm. We use the proposed algorithm and a time-to-digital converter (TDC) to obtain the number of the delay cells passed within one period of the input clock. The codes from TDC will shift and control two delay lines to allow the circuit to operate over a wide frequency rage. The circuit was fabricated by the TSMC 0.18-µm CMOS process. It can operate from 100MHz to 600MHz frequency. The acceptable duty cycle of the input clock ranges from 40% to 70%. The simulated locked time needs 28 cycles for 1.2GHz input signal.
The second one is a 200-1300 MHz all-digital duty-cycle programmable circuit using gated ring oscillator TDC. The gated ring oscillator TDC is used to detect the period of the input clock and calculate the corresponding delay to generate output clock with the desired duty cycle. A duty-cycle setting circuit calculates the desired output duty cycle without the need for a look-up table. Two kinds of delay lines are used to reduce hardware and maintain the same level accuracy compared with prior arts. The circuit was fabricated by the TSMC 0.18-µm CMOS process. The total power consumption for the entire duty-cycle programmable circuit is only 27mW, the input duty cycle ranges from 30 to 70%, and the programmable output duty cycle ranges from 31.25 to 68.75% in increments of 6.25%.
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