Improvement of Trench Gate MOSFET Gate Oxide Process

碩士 === 國立交通大學 === 工學院半導體材料與製程設備學程 === 102 === This paper is mainly investigate TEOS gas at the vertical furnace LPCVD method to grow UMOSFET gate oxide process, and improved to achieve production condition. Can be divided into three main parts: First, research of this TEOS LPCVD process when the pre...

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Main Authors: Hsu, Sheng-Tai, 徐盛泰
Other Authors: Wu, Yew-Chung Sermon
Format: Others
Language:zh-TW
Published: 2014
Online Access:http://ndltd.ncl.edu.tw/handle/99k854
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spelling ndltd-TW-102NCTU56860132019-05-15T21:50:57Z http://ndltd.ncl.edu.tw/handle/99k854 Improvement of Trench Gate MOSFET Gate Oxide Process 溝槽式閘極金氧半場效電晶體閘極氧化層製程之改善 Hsu, Sheng-Tai 徐盛泰 碩士 國立交通大學 工學院半導體材料與製程設備學程 102 This paper is mainly investigate TEOS gas at the vertical furnace LPCVD method to grow UMOSFET gate oxide process, and improved to achieve production condition. Can be divided into three main parts: First, research of this TEOS LPCVD process when the pressure controlled at 1.3torr and the vertical reaction chamber due to reaction gas concentration decreasing from bottom to top zone, this difference affect the deposition thickness distribution of reaction chamber top zone is bowl shaped and bottom zone is bull's-eye shaped, these wafer to wafer and within wafer non-uniform thickness distribution will limit process production capacity, Experiment to increase 22.8% wafer spacing method to improve the uniformity of the 800Å process of improving a rate of 58.7% at center area in reaction chamber, the best result for the uniformity of the reaction chamber are center and the center-bottom zone, set these two position to grow trench gate oxide process. Second, in order to reduce the on-resistance at UMOSFET, growth gate oxide layer in the trench which requires a uniform thickness of the sidewall and bottom side, to avoid too thin gate oxide layer and breakdown at this area, controlled TEOS flow rate / process pressure / temperature three parameters obtained the same bottom and sidewall oxide layer deposition rate. Finally, discussion the UMOSFET Loading Effect of its U-shaped trench structure when growth oxide layer process, as the number of wafers and density of the cells increases the reaction area will increases, this makes the area where the wafer deposition rate decreased, comparison the thickness differences under the same process conditions with use bare wafer, U-shaped trench structure wafer 25pcs loading effect to 6.49%, 50pcs to 12.09%, need to increase process temperature and deposition time to reach the target thickness. In order to achieve the purpose of production, at process monitor, use the monitor thickness control the products thickness, with the loading effect given different production conditions, depending on the number of U-shaped wafers. Wu, Yew-Chung Sermon 吳耀銓 2014 學位論文 ; thesis 46 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立交通大學 === 工學院半導體材料與製程設備學程 === 102 === This paper is mainly investigate TEOS gas at the vertical furnace LPCVD method to grow UMOSFET gate oxide process, and improved to achieve production condition. Can be divided into three main parts: First, research of this TEOS LPCVD process when the pressure controlled at 1.3torr and the vertical reaction chamber due to reaction gas concentration decreasing from bottom to top zone, this difference affect the deposition thickness distribution of reaction chamber top zone is bowl shaped and bottom zone is bull's-eye shaped, these wafer to wafer and within wafer non-uniform thickness distribution will limit process production capacity, Experiment to increase 22.8% wafer spacing method to improve the uniformity of the 800Å process of improving a rate of 58.7% at center area in reaction chamber, the best result for the uniformity of the reaction chamber are center and the center-bottom zone, set these two position to grow trench gate oxide process. Second, in order to reduce the on-resistance at UMOSFET, growth gate oxide layer in the trench which requires a uniform thickness of the sidewall and bottom side, to avoid too thin gate oxide layer and breakdown at this area, controlled TEOS flow rate / process pressure / temperature three parameters obtained the same bottom and sidewall oxide layer deposition rate. Finally, discussion the UMOSFET Loading Effect of its U-shaped trench structure when growth oxide layer process, as the number of wafers and density of the cells increases the reaction area will increases, this makes the area where the wafer deposition rate decreased, comparison the thickness differences under the same process conditions with use bare wafer, U-shaped trench structure wafer 25pcs loading effect to 6.49%, 50pcs to 12.09%, need to increase process temperature and deposition time to reach the target thickness. In order to achieve the purpose of production, at process monitor, use the monitor thickness control the products thickness, with the loading effect given different production conditions, depending on the number of U-shaped wafers.
author2 Wu, Yew-Chung Sermon
author_facet Wu, Yew-Chung Sermon
Hsu, Sheng-Tai
徐盛泰
author Hsu, Sheng-Tai
徐盛泰
spellingShingle Hsu, Sheng-Tai
徐盛泰
Improvement of Trench Gate MOSFET Gate Oxide Process
author_sort Hsu, Sheng-Tai
title Improvement of Trench Gate MOSFET Gate Oxide Process
title_short Improvement of Trench Gate MOSFET Gate Oxide Process
title_full Improvement of Trench Gate MOSFET Gate Oxide Process
title_fullStr Improvement of Trench Gate MOSFET Gate Oxide Process
title_full_unstemmed Improvement of Trench Gate MOSFET Gate Oxide Process
title_sort improvement of trench gate mosfet gate oxide process
publishDate 2014
url http://ndltd.ncl.edu.tw/handle/99k854
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