An Interleaved Zero-Voltage-Switching Power Factor Correction Circuit Applying FPGA
碩士 === 國立東華大學 === 電機工程學系 === 102 === This thesis proposes an interleaved ZVS (Zero-Voltage-Switching) power- factor-correction circuit. FPGA(Field Programmable Gate Array) is applied to coordinate the feedback signals to realize the control algorithm. The power stage is an interleaved boost converte...
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| Format: | Others |
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2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/m7j863 |