Width Minimization in the Single-Electron Transistor Array Synthesis
碩士 === 國立清華大學 === 資訊工程學系 === 102 === Power consumption has become one of the primary challenges to meet the Moore’s law. For reducing power consumption, Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore’s law due to its ultra-low pow...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/53188790540861651573 |