A Reduced-Complexity Layered Decoder Architecture for High Rate QC-LDPC Codes
碩士 === 國立清華大學 === 電機工程學系 === 102 === The conventional layered decoder for LDPC codes usually adopt serial check node units to reduce the area cost, but this way requires an additional variable-to-check (V2C) FIFO and the area of this FIFO may be very large when high rate codes are used. This thesis...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2013
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/04069661208295621518 |