A Reduced-Complexity Layered Decoder Architecture for High Rate QC-LDPC Codes
碩士 === 國立清華大學 === 電機工程學系 === 102 === The conventional layered decoder for LDPC codes usually adopt serial check node units to reduce the area cost, but this way requires an additional variable-to-check (V2C) FIFO and the area of this FIFO may be very large when high rate codes are used. This thesis...
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ndltd-TW-102NTHU54420292015-10-13T22:57:41Z http://ndltd.ncl.edu.tw/handle/04069661208295621518 A Reduced-Complexity Layered Decoder Architecture for High Rate QC-LDPC Codes 針對高碼率之類循環低密度奇偶校驗碼的低複雜度階層式解碼器 Hu, Jyun-Kai 胡鈞凱 碩士 國立清華大學 電機工程學系 102 The conventional layered decoder for LDPC codes usually adopt serial check node units to reduce the area cost, but this way requires an additional variable-to-check (V2C) FIFO and the area of this FIFO may be very large when high rate codes are used. This thesis presents a decoder architecture by rearranging the processing order, and the proposed layered decoder stores V2C extrinsic information instead of log-likelihood ratio (LLR) values. No additional FIFO is required for the updating after the serial operation. In addition, three methods about scheduling and resource binding are discussed to resolve the bank conflict of the proposed decoder architecture. For the LDPC code with the code length 4 kB and the code rate 0.9, approximate 22% of the total area is reduced without performance loss. After implemented in 90-nm CMOS process, the proposed LDPC decoder can achieve a throughput of 5.87 Gb/s with an area of 6.46 mm². Ueng, Yeong-Luh 翁詠祿 2013 學位論文 ; thesis 39 en_US |
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碩士 === 國立清華大學 === 電機工程學系 === 102 === The conventional layered decoder for LDPC codes usually adopt serial check node units to reduce the area cost, but this way requires an additional variable-to-check (V2C) FIFO and the area of this FIFO may be very large when high rate codes are used. This thesis presents a decoder architecture by rearranging the processing order, and the proposed layered decoder stores V2C extrinsic information instead of log-likelihood ratio (LLR) values. No additional FIFO is required for the updating after the serial operation. In addition, three methods about scheduling and resource binding are discussed to resolve the bank conflict of the proposed decoder architecture. For the LDPC code with the code length 4 kB and the code rate 0.9, approximate 22% of the total area is reduced without performance loss. After implemented in 90-nm CMOS process, the proposed LDPC decoder can achieve a throughput of 5.87 Gb/s with an area of 6.46 mm².
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author2 |
Ueng, Yeong-Luh |
author_facet |
Ueng, Yeong-Luh Hu, Jyun-Kai 胡鈞凱 |
author |
Hu, Jyun-Kai 胡鈞凱 |
spellingShingle |
Hu, Jyun-Kai 胡鈞凱 A Reduced-Complexity Layered Decoder Architecture for High Rate QC-LDPC Codes |
author_sort |
Hu, Jyun-Kai |
title |
A Reduced-Complexity Layered Decoder Architecture for High Rate QC-LDPC Codes |
title_short |
A Reduced-Complexity Layered Decoder Architecture for High Rate QC-LDPC Codes |
title_full |
A Reduced-Complexity Layered Decoder Architecture for High Rate QC-LDPC Codes |
title_fullStr |
A Reduced-Complexity Layered Decoder Architecture for High Rate QC-LDPC Codes |
title_full_unstemmed |
A Reduced-Complexity Layered Decoder Architecture for High Rate QC-LDPC Codes |
title_sort |
reduced-complexity layered decoder architecture for high rate qc-ldpc codes |
publishDate |
2013 |
url |
http://ndltd.ncl.edu.tw/handle/04069661208295621518 |
work_keys_str_mv |
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