A Reduced-Complexity Layered Decoder Architecture for High Rate QC-LDPC Codes

• Main Authors: Hu, Jyun-Kai, 胡鈞凱
• Other Authors: Ueng, Yeong-Luh
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/04069661208295621518

碩士 === 國立清華大學 === 電機工程學系 === 102 === The conventional layered decoder for LDPC codes usually adopt serial check node units to reduce the area cost, but this way requires an additional variable-to-check (V2C) FIFO and the area of this FIFO may be very large when high rate codes are used. This thesis presents a decoder architecture by rearranging the processing order, and the proposed layered decoder stores V2C extrinsic information instead of log-likelihood ratio (LLR) values. No additional FIFO is required for the updating after the serial operation. In addition, three methods about scheduling and resource binding are discussed to resolve the bank conflict of the proposed decoder architecture. For the LDPC code with the code length 4 kB and the code rate 0.9, approximate 22% of the total area is reduced without performance loss. After implemented in 90-nm CMOS process, the proposed LDPC decoder can achieve a throughput of 5.87 Gb/s with an area of 6.46 mm².