Robust Memory Circuits for VDDmin, Speed and Power Improvement
博士 === 國立清華大學 === 電機工程學系 === 102 === Supply-voltage (VDD) scaling techniques are often employed in low power Sys-tem-on-Chip (SoC) design; however, adverse impacts such as voltage-dependent timing skews and small sensing headroom have become increasingly significant on memory circuits. In this diss...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2014
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/75227874408037352439 |