Single-Loop Clock Data Recovery and Transformer-Coupled Current SerDes for High Speed Transmission Interface
博士 === 國立清華大學 === 電機工程學系 === 102 === The thesis proposes a serializer-and-deserializer (SerDes) with a clock and data recovery (CDR) to achieve high speed data processing for the wire-line communication system. The proposed 2:1 MUX and 1:2 DEMUX design deals with the maximum 40 Gb/s data transmissio...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/50323208023667754914 |