Single-Loop Clock Data Recovery and Transformer-Coupled Current SerDes for High Speed Transmission Interface

• Main Authors: Chen, Fan-Ta, 陳煥達
• Other Authors: Wu, Jen-Ming
• Format: Others
• Language: en_US
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/50323208023667754914

博士 === 國立清華大學 === 電機工程學系 === 102 === The thesis proposes a serializer-and-deserializer (SerDes) with a clock and data recovery (CDR) to achieve high speed data processing for the wire-line communication system. The proposed 2:1 MUX and 1:2 DEMUX design deals with the maximum 40 Gb/s data transmission rate. A transformer-coupled current (TCC) schematics is designed to more drain current and less supply voltage than the current-mode-logic (CML). The two chips are implemented in 65 nm standard CMOS technology and consume sub-hundred milliwatt operation power at the supply voltage of 0.8-V. The measured serialized-and-deserialized 40-Gb/s PRBS of 2^7–1 verify the function of SerDes interface. The proposed linear-type CDR design operates at full-rate data of 2.56/3.2Gb/s. An Ex-tended Phase Detector (EPD) circuit is proposed to replace the Hogge`s PD. The CDR circuit is fabricated in a 0.18μm 1P6M CMOS process in an area of 0.8×1.0 mm^2. This CDR chip exhibits a low jitter performance of 2.12 ps RMS in the recovered clock and a BER is 3.5 × 10^-9 with PRBS of 2^31–1 sequence. The power consumption is 136mW with a 1.8V supply. The proposed binary-type CDR design operates at full-rate 10 Gb/s data. A rotational phase frequency detector (RPFD) is proposed to realize reference-less CDR. The single-loop CDR is fabricated in TSMC mixed-signal 1P9M 90-nm standard CMOS process with overall die size of 0.71-mm^2. With input 10-Gb/s data of a 2^31–1 PRBS, the CDR tracks free running clock over the capture range of 1.48 GHz and locks in the acquisition time of 20 μs. At the same time, the peak-to-peak jitter shows only 5.0 ps in the recovered clock and exhibits 15.11 ps in the recovered data. The measured chip consumes 92 mW with 1.0-V supply voltage.