| Summary: | 碩士 === 國立臺北大學 === 通訊工程研究所 === 102 === In recent years, Negated AND (NAND) flash memory has been widely used as a medium for many storage systems, such as Solid State Drives (SSD). Most of NAND flash memory manufacturers scale down the manufacture process and stored more bits in each cell to lower cost. However, the reliability of stored data has become a critical issue since the scaled feature size lowers the number of electrons at each floating-gate while increases the Cell-to- Cell Interference (CCI). Besides, flash cell leaking charge over time also affects the reliability of the NAND flash memory. Therefore, we need more powerful Error Correcting Code (ECC) to promotion reliability such as Low-Density Parity Check (LDPC) codes. In this work, we develop an experimental instrument for Toshiba 19nm Triple Level Cell (TLC) NAND flash memory and observe the error characteristic in different simulation environment. In order to observe different amounts error characterization, we attempt to put different amounts of pilot into one page and collect these pilot results to calculate mean, variance and standard deviation. The threshold voltage will be changed when error characterization was happening in flash memory. We investigate the threshold voltage optimization by calculating the Mutual Information (MI) in Non-Gaussian distribution. The values of the threshold voltage are optimized by Maximizing Mutual Information (MMI) between two inputs and four outputs
of the three reads per cell under different situation.
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