Design and Implementation of a Stochastic ARM Core with Circuit Level Recovery Mechanism
碩士 === 國立臺灣大學 === 電子工程學研究所 === 102 === In this Thesis, we present a new central processor unit (CPU) architecture, which is able to use the whole timing margin and work in a more power efficient way. In advanced process, the process variation is too large to handle. Thus, manufacturers make the slac...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/18183883132461486960 |