Simulation and Analysis for Signal Integrity Issues of High-Speed Memory Interface Signal
碩士 === 國立臺灣科技大學 === 自動化及控制研究所 === 102 === Due to the increasing complexity of electronic product features and constant improvement of data rate, DDR interface design has become more demanding. In order to solve the design process problem of signal quality and timing sequence, we must satisfy the n...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/57053887091162492130 |