High Effciency Decoder Implementation of Latin Squares LDPC Codes
碩士 === 國立臺灣科技大學 === 電機工程系 === 102 === This thesis realizes the hardware architecture of the LDPC decoder, where the (9241,8240) LDPC code is constructed based on the Latin Square with code rate 0.89. The variable-node-centric sequential scheduling (VSS) technology is adopted to reduce hardware compl...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/60138536563924570522 |