An All Digital Phase-Locked Loop with Novel Phase and Frequency Error Compensation
碩士 === 國立臺灣科技大學 === 電機工程系 === 102 === This thesis presents a phase-frequency error compensation mechanism for an all digital phase-locked loop (ADPLL). First, a novel digital-controlled oscillator (DCO) was designed. This DCO possesses 8 period vs. control code transfer curves with good linearity. W...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/51873907499729226395 |