Design of Adaptive Instruction Codec Architecture for Network-on-Chip
碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 102 === The multicore system-on-chip (SoC) rapid development in recently. Messages exchanging between Processing Elements (PEs) are quite frequently. When using the traditional bus architecture cannot be requirement of the high performance. The Network-on-Chip (NoC)...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2014
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/j84g4m |