Design of All-Digital Burst-Mode Clock and Data Recovery Circuit
碩士 === 國立雲林科技大學 === 電機工程系 === 102 === In this thesis, the design of the burst mode data clock recovery (CDR) circuit is proposed with the all-digital technique. It is achieved completely by using the standard cell library. CDR can receive the data transmitted in the burst mode. The recovered clock...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/prd67g |