| Summary: | 碩士 === 國立雲林科技大學 === 電機工程系 === 102 === In this thesis, the design of the burst mode data clock recovery (CDR) circuit is proposed with the all-digital technique. It is achieved completely by using the standard cell library. CDR can receive the data transmitted in the burst mode. The recovered clock must be re-aligned with the input data. At the half-rate operation, the output data can be recovered and triggered with the aid of double-edge (both positive and negative edges) of the recovered clock. Therefore, the frequency of the recovered clock is only half of the data bit rate. In the all-digital control type, the binary codes decide the output clock frequency of oscillator so as to replace the voltage control of the analog type. When the circuit starts to work, the MSB codes of the output clock frequency from the oscillator is set initially by the Time-to-Digital Converter. Then, the LSB codes is tuned by up/down counter to adjust the cycle time finely. In this manner, the frequency error of the recovered clock can be corrected.
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