An All-Digital Burst-Mode Clock and Data Recovery Circuit
碩士 === 國立雲林科技大學 === 電機工程系碩士班 === 102 === This thesis presents the work of an all-digital half-rate burst-mode clock and data recovery circuit (CDR). Since it possesses the capability of realigning the recovered clock from the input data, this clock and data recovery circuit can be used to retiming t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/10191076709367380635 |