Low-Power Physical Design Optimization with Multi-Bit and Error-Tolerant Registers for Nanometer Integrated Circuits
博士 === 國立中正大學 === 電機工程研究所 === 103 === Power/thermal minimization has been becoming one of the most important objectives in the design of modern system on chips (SOCs) which integrate huge numbers of transistors. High power/thermal dissipation of an SOC may degrade product lifetime and reliability. T...
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| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/9s38y4 |