| Summary: | 博士 === 國立中正大學 === 電機工程研究所 === 103 === Power/thermal minimization has been becoming one of the most important objectives in the design of modern system on chips (SOCs) which integrate huge numbers of transistors. High power/thermal dissipation of an SOC may degrade product lifetime and reliability. To extend the battery duration and lifetime of the handheld SOC, one of the greatest design challenges is the ultra-low-power design for an SoC. In order to optimize the power consumption of an SoC more effectively, several low-power design techniques are proposed to reduce the clock power since it accounts for a large proportion of total power of an SoC. However, applying these techniques may induce design-related issues, including timing and placement density. Moreover, several advanced challenges, such as crosstalk effect and reliability issue, should also be considered due to the advanced process technology. Considering these requirements when applying low-power design techniques can effectively reduce the probability of functional failures and improve the circuit performance.
In this dissertation, we introduce the low-power design techniquesincluding multibit flip-flops (MBFFs) and time-borrowing-and-local-boosting (TBLB) resilient circuits to optimize the clock power consumption. To further satisfy and consider the most important design constraints and advanced requirements, including placement density, timing, wirelength minimization, crosstalk effect, and reliability issue, we propose novel electronic design automation (EDA) methodologies that individually integrate MBFFs and TBLB resilient circuits into existing design flow. This dissertation will cover four different parts, including: (1) post-placement power optimization with multi-bit flip-flops, (2) crosstalk-aware multi-bit flip-flop generation for power optimization, (3) clock-tree aware multi-bit flip-flop generation during placement for power optimization, and (4) reliabilityaware physical synthesis for low-power time-borrowing-and-local-boosting resilient circuits.
Experimental results show that our approaches are very effective to optimize the power consumption while considering placement density and timing constraints. In addition, it can achieve the best performance and improvement in wirelength minimization, crosstalk effect, and reliability issue.
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