A High Throughput Video Transform Architecture for High Efficiency Video Coding (HEVC) Applications

• Main Authors: Yi-Fan Ko, 柯奕帆
• Other Authors: Yuan-Ho Chen
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/jf28t5

碩士 === 中原大學 === 資訊工程研究所 === 103 === In this paper, a hardware design which can support for High Efficiency Video Coding (HEVC) Inverse Discrete Cosine Transform (IDCT) for 32×32 Transform Unit (TU) sizes is proposed and is implemented by a using single 1-D IDCT core with a transpose memory to achieve low cost design. The proposed 1-D IDCT core employs 16 calculating paths to achieve a high throughput rate and is implemented by a 1-D inverse transform core which can calculate 1st-D and 2nd-D data simultaneously in 32 parallel paths. The proposed 2-D transform core has a throughput rate of 2-Gpels/s with 337k gate counts when implemented into the TSMC 90nm CMOS technology.