A 10-bit 20MS/s Two-Step SAR Analog to Digital Converter

碩士 === 中原大學 === 電子工程研究所 === 103 === This paper proposes a Two-Step Successive-Approximation Analog to Digital Converter structure technique to reduce the total capacitance of the DAC capacitor network (The dominant source of the layout area of SAR ADCs), the settling time of the ADC circuit and the...

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Bibliographic Details
Main Authors: Yi-Wei Huang, 黃奕瑋
Other Authors: Chun-Chieh Chen
Format: Others
Language:zh-TW
Published: 2015
Online Access:http://ndltd.ncl.edu.tw/handle/26598858861256164197