| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 103 === This paper proposes a Two-Step Successive-Approximation Analog to Digital Converter structure technique to reduce the total capacitance of the DAC capacitor network (The dominant source of the layout area of SAR ADCs), the settling time of the ADC circuit and the switching energy of the capacitor network. In addition, this project also analyzes the parasitic capacitance of the circuit and summarizes an optimization design procedure of Two Step Successive-Approximation Analog-to-Digital Converters.
In this work, a 10-bit 20MS/s two-step successive approximation register analog to digital converter is proposed by using monotonic capacitor switching procedure. Design platform is TSMC 0.18μm 1P6M CMOS process. The power consumption of this work is 23.4mW at 1.8V power supply. This converter achieves SNDR 56.11dB, 9.03 Effective Number of Bits(ENOB). The Figure of Merit(FOM) is 2.238 pJ/conversion-step. The chip area is 1.175mm×1.175mm, and the core area is 0.360mm×0.375mm.
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