A 10-bit 20MS/s Two-Step SAR Analog to Digital Converter
碩士 === 中原大學 === 電子工程研究所 === 103 === This paper proposes a Two-Step Successive-Approximation Analog to Digital Converter structure technique to reduce the total capacitance of the DAC capacitor network (The dominant source of the layout area of SAR ADCs), the settling time of the ADC circuit and the...
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ndltd-TW-103CYCU54280222016-08-19T04:10:33Z http://ndltd.ncl.edu.tw/handle/26598858861256164197 A 10-bit 20MS/s Two-Step SAR Analog to Digital Converter 一個十位元每秒兩千萬取樣頻率之二階逐漸趨近式類比數位轉換器 Yi-Wei Huang 黃奕瑋 碩士 中原大學 電子工程研究所 103 This paper proposes a Two-Step Successive-Approximation Analog to Digital Converter structure technique to reduce the total capacitance of the DAC capacitor network (The dominant source of the layout area of SAR ADCs), the settling time of the ADC circuit and the switching energy of the capacitor network. In addition, this project also analyzes the parasitic capacitance of the circuit and summarizes an optimization design procedure of Two Step Successive-Approximation Analog-to-Digital Converters. In this work, a 10-bit 20MS/s two-step successive approximation register analog to digital converter is proposed by using monotonic capacitor switching procedure. Design platform is TSMC 0.18μm 1P6M CMOS process. The power consumption of this work is 23.4mW at 1.8V power supply. This converter achieves SNDR 56.11dB, 9.03 Effective Number of Bits(ENOB). The Figure of Merit(FOM) is 2.238 pJ/conversion-step. The chip area is 1.175mm×1.175mm, and the core area is 0.360mm×0.375mm. Chun-Chieh Chen 陳淳杰 2015 學位論文 ; thesis 80 zh-TW |
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碩士 === 中原大學 === 電子工程研究所 === 103 === This paper proposes a Two-Step Successive-Approximation Analog to Digital Converter structure technique to reduce the total capacitance of the DAC capacitor network (The dominant source of the layout area of SAR ADCs), the settling time of the ADC circuit and the switching energy of the capacitor network. In addition, this project also analyzes the parasitic capacitance of the circuit and summarizes an optimization design procedure of Two Step Successive-Approximation Analog-to-Digital Converters.
In this work, a 10-bit 20MS/s two-step successive approximation register analog to digital converter is proposed by using monotonic capacitor switching procedure. Design platform is TSMC 0.18μm 1P6M CMOS process. The power consumption of this work is 23.4mW at 1.8V power supply. This converter achieves SNDR 56.11dB, 9.03 Effective Number of Bits(ENOB). The Figure of Merit(FOM) is 2.238 pJ/conversion-step. The chip area is 1.175mm×1.175mm, and the core area is 0.360mm×0.375mm.
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author2 |
Chun-Chieh Chen |
author_facet |
Chun-Chieh Chen Yi-Wei Huang 黃奕瑋 |
author |
Yi-Wei Huang 黃奕瑋 |
spellingShingle |
Yi-Wei Huang 黃奕瑋 A 10-bit 20MS/s Two-Step SAR Analog to Digital Converter |
author_sort |
Yi-Wei Huang |
title |
A 10-bit 20MS/s Two-Step SAR Analog to Digital Converter |
title_short |
A 10-bit 20MS/s Two-Step SAR Analog to Digital Converter |
title_full |
A 10-bit 20MS/s Two-Step SAR Analog to Digital Converter |
title_fullStr |
A 10-bit 20MS/s Two-Step SAR Analog to Digital Converter |
title_full_unstemmed |
A 10-bit 20MS/s Two-Step SAR Analog to Digital Converter |
title_sort |
10-bit 20ms/s two-step sar analog to digital converter |
publishDate |
2015 |
url |
http://ndltd.ncl.edu.tw/handle/26598858861256164197 |
work_keys_str_mv |
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