TSV-aware Fixed-outline Floorplanning Methodology for 3D ICs
碩士 === 國立成功大學 === 電機工程學系 === 103 === A three-dimensional integrated circuit (3D IC) which uses through silicon vias (TSVs) as inter-die connections is one of the promising 3D integration technologies to break through bottlenecks faced by a 2D IC. However, TSVs are like double-edged swords. Despite s...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/19909715997141132183 |