FPGA Implementation of an H.264 Baseline Hardware Decoder
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 103 === In this thesis, we present the design of an H.264/AVC Hardware Decoder IP for a Xilinx Zynq 7020 FPGA platform. The behavior of the IP is as follows. The Hardware decoder IP will read the encoded H.264/AVC bitstream data from the DDR SDRAM using the AXI bus p...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/16970837550669985477 |