Optimization Methodologies of Using On-Chip Hardware Process Monitors for Speed Binning

碩士 === 國立交通大學 === 電子工程學系電子研究所 === 103 === In this work, an optimization methodologies of using on-chip hardware process monitors for speed binning is proposed. A flow of composed of SDF-modifying technique and model-fitting framework is used to generate the simulated data and analysis where and how...

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Main Authors:	Shen, Heng-Cheng, 沈桓丞
Other Authors:	Chao, Chia-Tso
Format:	Others
Language:	en_US
Published:	2014
Online Access:	http://ndltd.ncl.edu.tw/handle/34681536648402676057

id	ndltd-TW-103NCTU5428060
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spelling	ndltd-TW-103NCTU54280602016-10-23T04:12:11Z http://ndltd.ncl.edu.tw/handle/34681536648402676057 Optimization Methodologies of Using On-Chip Hardware Process Monitors for Speed Binning 使用晶片內部硬體製程監控器作速度分級之最佳化技巧 Shen, Heng-Cheng 沈桓丞碩士國立交通大學電子工程學系電子研究所 103 In this work, an optimization methodologies of using on-chip hardware process monitors for speed binning is proposed. A flow of composed of SDF-modifying technique and model-fitting framework is used to generate the simulated data and analysis where and how many should we place hardware process monitors. The proposed guide line for on-chip hardware process monitors placement shows better efficiency than greedy method. The mean error and maximum error is reduced over 50% in different parameter of process variation. A comparison of different method of speed binning is also presented. ii Chao, Chia-Tso 趙家佐 2014 學位論文 ; thesis 26 en_US
collection	NDLTD
language	en_US
format	Others
sources	NDLTD
description	碩士 === 國立交通大學 === 電子工程學系電子研究所 === 103 === In this work, an optimization methodologies of using on-chip hardware process monitors for speed binning is proposed. A flow of composed of SDF-modifying technique and model-fitting framework is used to generate the simulated data and analysis where and how many should we place hardware process monitors. The proposed guide line for on-chip hardware process monitors placement shows better efficiency than greedy method. The mean error and maximum error is reduced over 50% in different parameter of process variation. A comparison of different method of speed binning is also presented. ii
author2	Chao, Chia-Tso
author_facet	Chao, Chia-Tso Shen, Heng-Cheng 沈桓丞
author	Shen, Heng-Cheng 沈桓丞
spellingShingle	Shen, Heng-Cheng 沈桓丞 Optimization Methodologies of Using On-Chip Hardware Process Monitors for Speed Binning
author_sort	Shen, Heng-Cheng
title	Optimization Methodologies of Using On-Chip Hardware Process Monitors for Speed Binning
title_short	Optimization Methodologies of Using On-Chip Hardware Process Monitors for Speed Binning
title_full	Optimization Methodologies of Using On-Chip Hardware Process Monitors for Speed Binning
title_fullStr	Optimization Methodologies of Using On-Chip Hardware Process Monitors for Speed Binning
title_full_unstemmed	Optimization Methodologies of Using On-Chip Hardware Process Monitors for Speed Binning
title_sort	optimization methodologies of using on-chip hardware process monitors for speed binning
publishDate	2014
url	http://ndltd.ncl.edu.tw/handle/34681536648402676057
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Optimization Methodologies of Using On-Chip Hardware Process Monitors for Speed Binning

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